1. Field of the Invention
The present invention relates generally to a method and arrangement for detecting a framing bit sequence in a digital data communications system, and more specifically to such a method and arrangement by which a plurality of frame bit sequences can be rapidly detected and communication established. The present invention is concerned with a digital communications system wherein a transmitted bit stream is divided into a plurality of frames each of which is identified by a frame bit sequence included therein. Each frame bit sequence precedes data bit stream within the corresponding frame.
2. Description of the Prior Art
A circuit for detecting frame bit sequences is used to establish synchronous condition between a data terminal equipment and a user/network interface interconnected by a two-wire transmission line (for example). The user/network interface is usually attached to an electronic exchange.
Before turning to the present invention it is deemed preferable to discuss a known framing bit sequence detecting arrangement with reference to FIGS. 1 to 4.
Merely for the convenience of description, it is assumed that: (a) each frame consists of 160 bits wherein 4 bits are assigned to a framing bit sequence, (b) the time duration of one frame is 1 ms, (c) the framing bit sequence is followed by data bits (viz. 156 bits) and (c) consecutive frames transmitted are ascertained by frame bit sequences "0000", "0001", "0010", "0011", "0100", . . .
As shown in FIG. 1, a framing bit sequence comparator 10 is provided which has two input terminals 12, 14. The data bit stream 13 transmitted in a manner divided in frames, is received at the input terminal 12, while a framing bit sequence 15 is applied to the input terminal 14 for detecting the framing bit sequence included in the frame transmitted.
In the event that the comparator 10 detects a bit sequence, included a bit stream applied to the input 12, which coincides a framing bit sequence applied to the input 14, the comparator 10 outputs a coincidence signal 16 assuming a high level (for example). The coincidence signal 16 is applied to a set terminal S of an RS flip-flop (FF) 18. In this case, the FF 18 issues a reset signal 20 to a reset terminal R of a clock counter 22. Thus, the counter 22 starts counting clock pulses CK applied to the clock terminal CK thereof via a terminal 24. The clock pulses CK are also applied to a clock terminal CK of each of differentiators 26, 28. Timing charts of the operation of each of the differentiators 26, 28 are shown in FIG. 3. Since the operation of the differentiator 26 (28) is well known in the art, further discussion will be deemed unnecessary.
The clock counter 22 issues a carry signal 30 which assumes a logic 1 at the time when counting up 160 clock pulses the number of which equals the number of bits of one frame.
A modulo-5 counter 34, which follows an AND gate 32, counts up if the signals 16 and 30 applied thereto assume a logic 1 simultaneously. Another AND gate 36 is supplied with the coincidence signal 16 via an invertor 38 at one of the two inputs thereof while receiving the frame count-up signal 30 at the other input. This means that a modulo-5 counter 40 counts up if the carry signal 30 from the counter 22 assumes a logic 1 and simultaneously the coincidence signal 16 assumes a logic 0. The operation of the modulo-5 counter 34 (40) is shown by timing charts in FIG. 2.
In the event that the counter 40 counts up to the maximum number thereof (viz., has counted from 0 to 4 in this particular case), the counter 40 issues a carry signal 42 (logic 1) at an output CA, which is applied to the differentiator 28 and also to a NOR gate 44 via an invertor 46. An output 48 of the differentiator 28 assumes a logic 1 and hence resets the modulo-5 counters 34, 40 via an OR gate 50. Further, the output 42 resets a SR flip-flop 52 in this case.
On the other hand, if the modulo-5 counter 34 counts up from 0 to 4, it issues a carry signal (logic 1) 54 at an output CA, which is applied to the differentiator 26 and also to the NOR gate 44. An output 54 of the differentiator 26 assumes a logic 1 and hence resets the modulo-5 counters 34, 40 via the OR gate 50. Further, the output 54 sets the SR flip-flop (FF) 52, which in turn issues a synchronization detection signal 58 assuming a logic 1 indicating that synchronization has been established.
The operation of the FIG. 1 arrangement will further be described with reference to FIG. 4.
It is assumed that the comparator 10 detects a bit sequence "0000" in the bit stream 13 which coincides with a framing bit sequence 15 assuming "0000" at a time point A. Accordingly, the signal 16 assumes a logic 1. In this instance, the carry signal 30 from the clock counter 22 remains to assume a logic 1 and, hence the state of the counter 34 changes from 0 to 1. However, the counter 40 remains unchanged. Since the content of the framing bit sequence 15 is advanced by one in response to a trailing edge of the carry signal 30, the comparator 10 stores the next framing bit sequence "0001" at a time point B. It is assumed that the comparator 10 detects, at a time point C, a bit sequence "0001" in the bit stream 13 which coincides with the framing bit sequence 15 assuming "0001". In this case, the content of each of the modulo-5 counters 40, 54 remains unchanged. Following this, the carry signal 30 from the clock counter 22 assumes a logic 1 at a time point D and, hence the counter 40 changes the state thereof from 0 to 1 in that the coincidence signal 16 assumes a logic 0 at the time point D.
Similarly, the modulo-5 counter 34 changes the state thereof from 1 to 2 at a time point E, after which it further changes the state thereof from 2 to 3 at a time point H. On the other hand, the modulo-5 counter 40 changes the state thereof from 1 to 2 at a time point F, from 2 to 3 at a time point G, and from 3 to 4 at a time point I. Since the modulo-5 counter 40 counts up to the maximum number 4, the counter 40 issues, at a time point J, the reset signal 42 which renders the counters 34, 40 to reset at a time point slightly later than the time point J. Thus, each of the counters 34, 40 returns to the initial state (viz., 0) as shown in FIG. 4.
In the event that the counter 34 returns to zero, the framing bit sequence 15 again assumes "0000" and advances the content by binary one in response to the trailing edge of the carry signal 30 issued from the clock counter 22. It is assumed that the comparator 10 detects a bit sequence "0000" in the bit stream 13 which coincides with a framing bit sequence 15 assuming "0000" at a time point K. Thus, the signal 16 assumes a logic 1. In this instance, the carry signal 30 from the clock counter 22 assumes a logic 1, so that the state of the counter 34 changes from 0 to 1. However, the counter 40 remains unchanged. Following this, it is assumed that the coincidence signal 16 assumes a logic 1 at time points L, M and N as illustrated in FIG. 4, and the counter 34 counts up from 1 to 4.
At the time point P, which is approximately one clock later from the time point N, a carry signal 54 assuming a logic 1 (denoted by numeral 70) is produced by the modulo-5 counter 34. Accordingly, the synchronization detection signal 58 assumes a logic 1 at the time point P, indicating that a synchronization has been established. After the time point P, the comparator 10 detects bit sequences "0000", "0101", . . . , as shown in FIG. 4. It is a usual practice to transmit meaningless data following each framing bit sequence until the transmitter is informed of the establishment of the synchronization or until a time interval deemed sufficient to establish the synchronization.
However, the above-mentioned prior art has encountered the problem in that it takes an undesirably long time until the reset signal 42 assumes a logic 1 (for example, at the time point J). In more specific terms, it is extremely rare that the modulo-5 counter 34 counts up and allows the FF 52 to issue a logic 1 at an early stage of initially operating the system. Accordingly, it is highly desirable to retry the search for the framing bit sequence by resetting the modulo-5 counters 34, 40. However, there is a high probability that the comparator 10 will detect a bit sequence included in the bit stream 13 which is not located at the appropriate location, viz., the first 4-bit of each of the frames. Therefore, in the event that the same bit sequence erroneously detected at the comparator 10 appears at the same position of the following frames, it takes a long time duration until the counter 40 counts up and resets the modulo-5 counters 34, 40.